1. Field of the Invention
The present invention relates to a voltage generation circuit, and particularly, to a voltage generation circuit for a mask-programmed read only memory (called a "mask ROM" hereinafter) configured to store information of three or more values in one bit, namely in one memory cell.
2. Description of Related Art
In order to elevate the integration density in the mask ROM, a multivalued cell has been proposed which can store the information amount of more than two values, in one memory cell transistor. For example, Japanese Patent Application Pre-examination Publication No. JP-A-62-204496 proposed a multivalue semiconductor memory, which includes a voltage generating circuit, a plurality of transistors, and a transistor receiving an output voltage of each of the plurality of transistors, for step-by-step increasing or decreasing the level of a word line, for the purpose of surely reading out the multivalued information stored in the memory cell.
FIG. 5 shows a block diagram of one example of the prior art circuit structure of an X decoder for a multivalued-cell type mask ROM. Referring to FIG. 5, the shown X decoder is constituted of a voltage generating circuit 501 and a word line decoding circuit 502.
The voltage generating circuit 501 includes a first reference voltage generating circuit 404, a first differential amplifying circuit 401, a first transfer gate circuit 504, a second reference voltage generating circuit 405, a second differential amplifying circuit 402, a second transfer gate circuit 505, a third reference voltage generating circuit 406, a third differential amplifying circuit 403, a third transfer gate circuit 506, and a first NMOS transistor Q507 for discharging, to a ground level, an output OUT501 (an output of the voltage generating circuit) which is connected in conunon to respective outputs of the first to third transfer gate circuits 504 to 506.
On the other hand, the word line decoding circuit 502 includes a fourth transfer gate circuit 507, a second NMOS transistor Q510 for discharging an output of the fourth transfer gate circuit 507 to the ground level when it is not selected, a fifth transfer gate circuit 508, a third NMOS transistor Q513 for discharging an output of the fifth transfer gate circuit 508 to the ground level when it is not selected, a sixth transfer gate circuit 509, a fourth NMOS transistor Q516 for discharging an output of the sixth transfer gate circuit 509 to the ground level when it is not selected. The outputs of the fourth to sixth transfer gate circuits 507 to 509 are connected to word lines WL501 to WL503, respectively.
FIG. 4 shows a detailed circuit construction of the voltage generating circuit 501. The first reference voltage generating circuit 404 is constituted of a first PMOS transistor Q401 and a fifth NMOS transistor Q402. The first PMOS transistor Q401 has a source terminal connected to a power supply terminal VCC, a gate terminal connected to receive an inverted chip enable signal CEB, and a drain terminal connected to an output CVOUT401 of the first reference voltage generating circuit 404. The fifth NMOS transistor Q402 has a source terminal connected to a ground terminal GND, and a gate terminal and a drain terminal connected in common to the output CVOUT401 of the first reference voltage generating circuit 404.
The first differential amplifying circuit 401 comprises a differential pair of transistors Q405 and Q406 having their respective sources connected in common to a constant current source transistor Q407, transistors Q403 and Q404 constituting a current mirror which acts as an active load for the differential pair, a transistor Q408 receiving an output of the differential pair, and a transistor Q409 connected in series with the transistor Q408 and rendered conductive when a non-inverted chip enable signal CE is active. One of a pair of inputs of the first differential amplifying circuit is connected to the output CVOUT401 of the first reference voltage generating circuit 404, and the other input of the first differential amplifying circuit is connected to receive an output VOUT401 of the differential amplifying circuit (voltage follower). Incidentally, the second and third differential amplifying circuits 402 and 403 are constituted similarly to the first differential amplifying circuit 401.
More specifically, the first differential amplifying circuit 401 includes a second PMOS transistor Q403, a third PMOS transistor Q404, a fourth PMOS transistor Q408, a sixth NMOS transistor Q405, a seventh NMOS transistor Q406, an eighth NMOS transistor Q407, and a ninth NMOS transistor Q409. Respective source terminals of the second PMOS transistor Q403, the third PMOS transistor Q404 and the fourth PMOS transistor Q408 are connected to the power supply terminal VCC. The second PMOS transistor Q403 has a gate terminal and a drain terminal connected in common to a terminal T401, and the third PMOS transistor Q404 has a gate terminal connected to the terminal T401, and a drain terminal connected to a terminal T403. The sixth NMOS transistor Q405 has a drain terminal connected to the terminal T401, a source terminal connected to a terminal T402, and a gate terminal connected to the output VOUT401 of the first differential amplifying circuit 401. The seventh NMOS transistor Q406 has a drain connected to the terminal T403, a source terminal connected to the terminal T402, and a gate terminal connected to the output CVOUT401 of the first reference voltage generating circuit.
The eighth NMOS transistor Q407 has a drain terminal connected to the terminal T402, a source terminal connected to the ground terminal GND and a gate terminal connected to receive the chip enable signal CE. The fourth PMOS transistor Q408 has a source connected to the power supply terminal VCC, a gate terminal connected to the terminal T403, and a drain terminal connected to the output VOUT401 of the first differential amplifying circuit 401. The ninth NMOS transistor Q409 has a source terminal connected to the ground terminal GND, a gate terminal connected to receive the chip enable signal CE, and a drain terminal connected to the output VOUT401 of the first differential amplifying circuit 401.
The second reference voltage generating circuit 405 is constituted of a fifth PMOS transistor Q410 and a tenth NMOS transistor Q411. The fifth PMOS transistor Q410 has a source terminal connected to the power supply terminal VCC, a gate terminal connected to receive the inverted chip enable signal CEB, and a drain terminal connected to an output CVOUT402 of the second reference voltage generating circuit. The tenth NMOS transistor Q411 has a source terminal connected to the ground terminal GND, and a gate terminal and a drain terminal connected in common to the output CVOUT402 of the second reference voltage generating circuit.
Next, the second differential amplifying circuit 402 includes a sixth PMOS transistor Q412, a seventh PMOS transistor Q413, an eighth PMOS transistor Q417, an eleventh NMOS transistor Q414, a twelfth NMOS transistor Q415, a thirteenth NMOS transistor Q416, and a fourteenth NMOS transistor Q418. Respective source terminals of the sixth PMOS transistor Q412, the seventh PMOS transistor Q413 and the eighth PMOS transistor Q417 are connected to the power supply terminal VCC. The sixth PMOS transistor Q412 has a gate terminal and a drain terminal connected in common to a terminal T404, and the seventh PMOS transistor Q413 has a gate terminal connected to the terminal T404, and a drain terminal connected to a terminal T406. The eleventh NMOS transistor Q414 has a drain terminal connected to the terminal T404, a source terminal connected to a terminal T405, and a gate terminal connected to the output VOUT402 of the second differential amplifying circuit 402. The twelfth NMOS transistor Q415 has a drain connected to the terminal T406, a source terminal connected to the terminal T405, and a gate terminal connected to the output CVOUT402 of the second reference voltage generating circuit. The thirteenth NMOS transistor Q416 has a drain terminal connected to the terminal T405, a source terminal connected to the ground terminal GND and a gate terminal connected to receive the chip enable signal CE. The eighth PMOS transistor Q417 has a source connected to the power supply Terminal VCC, a gate terminal connected to the terminal T406, and a drain terminal connected to the output VOUT402 of the second differential amplifying circuit 402. The fourteenth NMOS transistor Q418 has a source terminal connected to the ground terminal GND, a gate terminal connected to receive the chip enable signal CE, and a drain terminal connected to the output VOUT402 of the second differential amplifying circuit 402.
The third reference voltage generating circuit 406 is constituted of a ninth PMOS transistor Q419 and a fifteenth NMOS transistor Q420. The ninth PMOS transistor Q419 has a source terminal connected to the power supply terminal VCC, a gate terminal connected to receive the inverted chip enable signal CEB, and a drain terminal connected to an output CVOUT403 of the third reference voltage generating circuit. The fifteenth NMOS transistor Q420 has a source terminal connected to the ground terminal GND, and a gate terminal and a drain terminal connected in common to the output CVOUT403 of the third reference voltage generating circuit.
Next, the third differential amplifying circuit 403 includes a tenth PMOS transistor Q421, an eleventh PMOS transistor Q422, a twelfth PMOS transistor Q426, a sixteenth NMOS transistor Q423, a seventeenth NMOS transistor Q424, an eighteenth NMOS transistor Q425, and a nineteenth NMOS transistor Q427. Respective source terminals of the tenth PMOS transistor Q421, the eleventh PMOS transistor Q422 and the twelfth PMOS transistor Q426 are connected to the power supply terminal VCC. The tenth PMOS transistor Q421 has a gate terminal and a drain terminal connected in common to a terminal T407, and the eleventh PMOS transistor Q422 has a gate terminal connected to the terminal T407, and a drain terminal connected to a terminal T409. The sixteenth NMOS transistor Q423 has a drain terminal connected to the terminal T407, a source terminal connected to a terminal T408, and a gate terminal connected to the output VOUT403 of the third differential amplifying circuit 403. The seventeenth NMO.S transistor Q424 has a drain connected to the terminal T409, a source terminal connected to the terminal T408, and a gate terminal connected to the output CVOUT403 of the third reference voltage generating circuit. The eighteenth NMOS transistor Q425 has a drain terminal connected to the terminal T408, a source terminal connected to the ground terminal GND and a gate terminal connected to receive the chip enable signal CE. The twelfth PMOS transistor Q426 has a source connected to the power supply terminal VCC, a gate terminal connected to the terminal T409, and a drain terminal connected to the output VOUT403 of the third differential amplifying circuit 403. The nineteenth NMOS transistor Q427 has a source terminal connected to the ground terminal GND, a gate terminal connected to receive the chip enable signal CE, and a drain terminal connected to the output VOUT403 df the third differential amplifying circuit 403.
An operation of the prior art X decoder circuit shown in FIG. 5 for the multivalued-cell type mask ROM will be described with reference to the detailed circuit of the voltage generating circuit shown in FIG. 4 and a waveform diagram shown in FIG. 6 for illustrating the circuit operation.
Assuming that the threshold of the fifth NMOS transistor Q402 in the first reference voltage generating circuit 404 (FIG. 4) is Vt1 and a current driving capacity of the fifth NMOS transistor Q402 is sufficiently larger than that of the first PMOS transistor Q401, the potential of the output terminal CVOUT401 of the first reference voltage generating circuit 404 is substantially equal to Vt1.
The first differential amplifying circuit 401 receives the output CVOUT401 of the first reference voltage generating circuit 404, and becomes an equilibrated condition when the output VOUT401 of the first differential amplifying circuit 401 and the output CVOUT401 of the first reference voltage generating circuit 404 have become equal in potential. Accordingly, the potential of the output VOUT401 of the first differential amplifying circuit 401 becomes substantially equal to Vt1.
Assuming that the threshold of the tenth NMOS transistor Q411 in the second reference voltage generating circuit 405 is Vt2 and a current driving capacity of the tenth NMOS transistor Q411 is sufficiently larger than that of the fifth PMOS transistor Q410, the potential of the output terminal CVOUT402 of the second reference voltage generating circuit 405 is substantially equal to Vt2.
Since the second differential amplifying circuit 402 operates similarly to the first differential amplifying circuit 401, the potential of the output VOUT402 of the second differential amplifying circuit 402 becomes substantially equal to Vt2.
Assuming that the threshold of the fifteenth NMOS transistor Q420 in the third reference voltage generating circuit 406 is Vt3 and a current driving capacity of the fifteenth NMOS transistor Q420 is sufficiently larger than that of the ninth PMOS transistor Q419, the potential of the output terminal CVOUT403 of the third reference voltage generating circuit 405 is substantially equal to Vt3.
Since the third differential amplifying circuit 403 operates similarly to the first differential amplifying circuit 401, the potential of the output VOUT403 of the third differential amplifying circuit 403 becomes substantially equal to Vt3.
As mentioned above, in the circuit shown in FIG. 5, the output of the first differential amplifying circuit 401 is substantially equal to Vt1, the output of the second differential amplifying circuit 402 is substantially equal to Vt2, and the output of the third differential amplifying circuit 403 is substantially equal to Vt3. By supplying signals having waveforms as shown in FIG. 6, to a pair of inputs .phi.1 and .phi.1B of the first transfer gate circuit 504, a pair of inputs .phi.2 and .phi.2B of the first transfer gate circuit 505, and a pair of inputs .phi.3 and .phi.3B of the first transfer gate circuit 506, respectively, and also by supplying signals having waveforms as shown in FIG. 6, to a pair of inputs XMP1 and XMP1B of the fourth transfer gate circuit 507 of the word line decoding circuit 502, a pair of inputs XMP2 and XMP2B of the fifth transfer gate circuit 508 and a pair of inputs XMPn and XMPnB of the sixth transfer gate circuit 509, respectively, the potential of the first word line WL501 can be changed in a stepped form as shown in FIG. 6.
However, the above mentioned prior art has the following problems:
A first problem is that, in the X decoder circuit shown in FIG. 5, a difference (.DELTA.V) between the generated gate voltage and the threshold voltage of the memory cell transistor is different from one word line to another in accordance with the position of the word line as shown in FIG. 8, with the result that the sense speed becomes low dependently upon the position of the memory cell to be read out.
The reason for this is as follows: In the second reference voltage generating circuit 405 shown in FIG. 4, assuming that the threshold of the tenth NMOS transistor Q411 is Vt2 and the current driving capacity of the tenth NMOS transistor Q411 is sufficiently larger than that of the fifth PMOS transistor Q410, the potential of the output terminal CVOUT402 of the second reference voltage generating circuit 405 becomes substantially equal to Vt2. Therefore, the output potential of the second differential amplifying circuit shown in FIG. 5 becomes substantially equal to Vt2. If the inputs .phi.2 and .phi.2B of the second transfer gate circuit 505 are supplied with a high level and a low level, respectively, the output OUT501 of the voltage generating circuit 501 also becomes substantially equal to Vt2.
Here, in a memory cell matrix shown in FIG. 7, it is assumed that all of a first memory cell transistor Q733, a second memory cell transistor Q726, a third memory cell transistor Q719, a fourth memory cell transistor Q712 and a fifth memory cell transistor Q705 were manufactured to have the same threshold Vt1. Actually, however, the threshold of the first memory cell transistor Q733 becomes about Vt1, the threshold of the second memory cell transistor Q726 becomes about Vt1+.alpha.1, the threshold of the third memory cell transistor Q719 becomes about Vt1+.alpha.2, the threshold of the fourth memory cell transistor Q712 becomes about Vt1+.alpha.3, and the threshold of the fifth memory cell transistor Q705 becomes about Vt1+.alpha.4.
Here, .alpha.1, .alpha.2, .alpha.3 and .alpha.4 are variables changing dependently upon a parasite resistance of a source terminal of the second memory cell transistor Q726, the third memory cell transistor Q719, the fourth memory cell transistor Q712 and the fifth memory cell transistor Q705, and the large-and-small relation of .alpha.1, .alpha.2, .alpha.3 and .alpha.4 is expressed by the following expression: EQU .alpha.1&lt;.alpha.2&lt;.alpha.3&lt;.alpha.4 (1)
As a result, the larger the source teriinal parasite resistance of the memory cell transistor is, the larger the apparent threshold of the memory cell transistor becomes.
The result of the above mentioned matter is shown in FIG. 8.
As seen by examining FIG. 8, the threshold changes in accordance with the position of the word line to which the gate terminal of the memory cell transistor is connected, and on the other hand, the output of the voltage generating circuit is at constant. Therefore, the sense speed changes dependently upon the position of the word line to which the gate terminal of the memory cell transistor is connected, and in the worst case, a reading error occurs.